1. Field of Invention
The present invention generally relates to semiconductor devices, and more particularly, to a semiconductor device in which a TEG (test elementary group) is inserted in a specified region of a wafer to conduct a pass-or-fail test for the wafer.
2. Description of Related Art
Generally, numerous steps are required to manufacture semiconductor devices, and therefore it is desirable to determine, at an initial stage of the process, as to whether a wafer is acceptable or defective, so that defective wafers can be removed from the manufacturing process. For this reason, a TEG (test elementary group), an element for wafer examination, may often be formed in a predetermined region of the wafer.
FIGS. 8(a) and 8(b) are schematics that show a wafer in which such a TEG is formed. The wafer 10 shown in FIG. 8(a) will be cut by dicing into small pieces to provide numerous individual chips 11. For this reason, as FIG. 8(b) shows, dicing lines 12, that serve as marks for the dicing, are drawn between the numerous chip regions. In this manner, regions on the wafer that divide the chip regions can be used for drawing marks or the like, and are therefore referred to as scribe regions. As shown in FIG. 8(b), the TEG is formed in a predetermined region 13 among the scribe regions. Hereafter, the region where the TEG is formed is referred to as a scribe TEG region.
In the related art, circuit elements, such as transistors, are formed in scribe TEG regions, and characteristics of the circuit elements themselves are measured to judge whether the wafers are acceptable or defective. FIG. 9 shows one example of the circuit element that is formed in a scribe TEG region in the related art semiconductor device.
In FIG. 9, two transistors Q1 and Q2 are shown as an example. Gates G of the transistors Q1 and Q2 are connected to a gate pad, and sources S thereof are connected to a source pad. Also, a drain D of the transistor Q1 is connected to a drain pad A, and a drain D of the transistor Q2 is connected to a drain pad B. Probes, which are connected to a measuring apparatus (IC tester or the like) through cables, are brought into contact with the pads, and characteristics of the transistors Q1 and Q2 are measured. This measurement is referred to as a DC examination in which a DC voltage is applied to the circuit elements, and DC voltage or DC current generated on the circuit elements are measured. A drain current IOFF during an OFF period, a drain current ION during an ON period, a gain coefficient xcex2, a gate-source threshold voltage VTH and the like can be listed as characteristics to be measured for the transistors.
A delay time in the circuit that is formed of a combination of multiple transistors in a chip that is actually used substantially changes according to changes in the parasitic capacitance and diffusion resistance in each of the elements. However, measurements of the parasitic capacitance and diffusion resistance of transistors formed in scribe TEG regions are difficult because the floating capacitance and loss resistance affect such measurements. Accordingly, for related art semiconductor devices, it is not possible to completely check, at an initial stage, whether a wafer is acceptable or defective, and an operational defect may then be discovered for the first time when chips are completed. This causes a problem in that the yield of chips is lowered in later manufacturing steps.
Also, in order to analyze steps that may have caused such operational defects, the AC examination is necessarily conducted on the completed chips, making the confirmation work more complicated.
In view of the above, the present invention provides a semiconductor device that enables determination of a wafer, at an initial stage, as to whether the wafer is acceptable or defective in the case of DC examinations for circuit elements and also AC examinations for circuit delay times and the like.
In order to address the problems described above, a semiconductor device in accordance with the present invention is equipped with (a) a semiconductor wafer including a plurality of chip regions in which a specified circuit is formed, and a scribe region to divide the plurality of chip regions, (b) a test circuit for wafer examination formed in the scribe region and formed of a plurality of transistors, and (c) an output pad formed in the scribe region and connected to the test circuit.
The semiconductor device in accordance with the present invention may further include an input pad that is formed in the scribe region and connected to the test circuit. In this case, the test circuit may include a plurality of serially connected inversion circuits. Alternatively, the test circuit may include a selector circuit that supplies a signal supplied from the input pad to a first output or a second output according to a control signal, a plurality of inverter circuits serially connected to a first output of the selector circuit, an output circuit that supplies, to the output pad, one of an output signal of the last stage of the plurality of inverter circuits and a second output signal of the selector circuit, and a control pad formed in the scribe region to input a control signal to the selector circuit. Alternatively, the test circuit may include a plurality of inverter circuits serially connected to the input pad, and an output circuit that produces an exclusive OR of an output signal of the last stage of the plurality of inverter circuits and an input signal supplied to the input pad, and supplies the same to the output pad.
Also, in the semiconductor device in accordance with the present invention, the test circuit may include a plurality of circuits that are connected in a loop, invert an input signal and output the same, and an output circuit that supplies an output signal of one of the plurality of circuits to the output pad. These circuits may include at least one NAND circuit, and the semiconductor device may further include a control pad that is formed in the scribe region to supply a control signal to one of inputs of the at least one NAND circuit.
In the above semiconductor devices, the plurality of transistors formed in the scribe region for wafer examination may include a transistor having the same configuration of a transistor formed in the chip regions. Also, in the case of a gate array, the plurality of transistors formed in the scribe region for wafer examination may form a cell having the same configuration of a basic cell formed in the chip regions.
In accordance with the invention, a test circuit formed of a plurality of transistors for wafer examination is formed in a scribe TEG region. As a result, pass or fail of a wafer can be determined in an initial stage in the case of DC examination for circuit elements and also AC examination for circuit delay times and the like. Also, the same circuit may be formed for different types, such that data can be compared among the different types. Further, the AC examination in each chip may possibly be omitted, which alleviates the burden for analysis in the AC examination.